FIG. 1 is a block diagram of a typical synchronous output buffer circuit 100, which includes boundary scan features that support IEEE standard 1149.1. Synchronous output buffer circuit 100 includes output registers 101-102, multiplexers 111-112, tri-state output buffer 120, logical AND gate 115 and inverter 116, which are connected as illustrated.
Signals used to implement the boundary scan features of synchronous output buffer circuit 100 include a boundary scan data signal (BS_D), a boundary scan output enable signal (BS_OE) and a boundary scan tri-state signal (BS_Tri). These boundary scan signals are well known to those of ordinary skill in the art. A mode control signal (MODE) is activated to enable a boundary scan mode (and de-activated to enable a normal operating mode). In the boundary scan mode, the activated MODE signal causes multiplexers 111 and 112 to route the boundary scan data signal BS_D and the boundary scan output enable signal BS_OE, respectively. The boundary scan data signal BS_D is applied to the data input terminal of tri-state output buffer 120. The boundary scan output enable signal BS_OE is applied to an input terminal of AND gate 115. The other input terminal of AND gate 115 is coupled to receive the inverse of the boundary scan tri-state signal BS_Tri from inverter 116. The output of AND gate 115 provides an output enable signal OEo to a control terminal of tri-state output buffer 120.
When the boundary scan tri-state signal BS_Tri is activated to a logic ‘1’ state, AND gate 115 provides an output enable signal OEo having a logic ‘0’ state. In response, tri-state output buffer 120 enters a high impedance state (to implement the HIGHZ boundary scan instruction).
When the boundary scan tri-state signal ES_Tri is de-activated to a logic ‘0’ state, AND gate 115 provides an output enable signal OEo having the same logic state as the boundary scan output enable signal BS_OE. If the boundary scan output enable signal BS_OE (and therefore the output enable signal OEo) has a logic ‘1’ state, then tri-state output buffer 120 drives received boundary scan data signal BS_D as the output data signal Q. The output data signal Q is driven off of the integrated circuit chip on which synchronous output buffer circuit 100 is located.
During normal operation of synchronous output buffer circuit 100, the MODE signal and the boundary scan tri-state signal BS_Tri are both de-activated to a logic ‘0’ state. Output registers 101 and 102 are coupled to receive a data signal Di and an output enable signal OEi, respectively, from the internal logic of the integrated circuit chip. Output registers 101 and 102 synchronously latch the applied signals Di and OEi, respectively, in response to rising edges of an output clock signal CLK. Output registers 101 and 102 provide the latched signals to multiplexers 111 and 112, respectively. The de-activated MODE signal causes multiplexer 111 to route the signal provided by output register 101 as the data signal Do. This data signal Do is provided to the input terminal of tri-state output buffer 120. The de-activated MODE signal also causes multiplexer 112 to route the signal latched in output register 102 to AND gate 115. The logic ‘0’ state of the boundary scan tri-state signal BS_Tri causes AND gate 115 to route the signal provided by multiplexer 112 as the output enable signal OEo. The output enable signal OEo is provided to the control terminal of tri-state output buffer 120. If the output enable signal OEo has a logic ‘1’ state, then tri-state output buffer 120 is enabled to drive the received data signal Do as the output signal Q.
In a double data rate (DDR) output interface, the output clock signal CLK switches at two times (2×) the frequency of the system clock signal (i.e., the clock signal that controls the internal logic of the integrated circuit chip). In addition, the synchronous output buffer circuit 100 and the internal logic of the integrated circuit chip are coupled to different power supplies. The power supply coupled to the synchronous output buffer circuit 100 typically exhibits a relatively wide voltage supply range (e.g., 1.4 to 1.9 Volts), while the power supply coupled to the internal logic is designed to exhibit a relative narrow voltage supply range (e.g., 1.7 to 1.9 Volts). Finally, the separate power supplies require that a voltage translation circuit (not shown) be included within the synchronous output buffer circuit 100.
To maximize performance at a system level, the skew among the output signals (‘output skew’) of a chip needs to be minimized. The system clock cycle time is increased by the amount of output skew. In the case of a DDR output, the system clock cycle time is increased by 2× the amount of output skew. Hence, controlling the output skew to a minimum is very important for high speed design.
Some issues relating to output skew have been resolved by prior art output buffer circuits. For example, the output skew has been reduced by using a balanced clock tree to route the output clock signal CLK, in combination with a delay locked loop (DLL) circuit to synchronize the output clock signal CLK with an input clock signal. In addition, output impedance matching circuits have been used to compensate for variations in output buffer strength, which occur with variations in data polarity, voltage and temperature.
However, some issues relating to output skew have not been resolved. For example, the delay from the rising edge of the output clock signal CLK to the time that the output data Q is provided (hereinafter referred to as the ‘CLK-to-Q delay’) involves 5 different paths within synchronous output buffer circuit 100. These different CLK-to-Q delays are introduced when: (1) the data signal Do causes the output signal Q to transition to a logic ‘1’ state, (2) the data signal Do causes the output signal Q to transition to a logic ‘0’ state, (3) the output enable signal OEo causes the output signal Q to transition to a logic ‘1’ state, (4) the output enable signal OEo causes the output signal Q to transition to a logic ‘0’ state, and (5) the output enable signal OEi causes the output signal Q to transition to a high impedance state (i.e., tri-state). Each of these five paths actually includes two sub-paths, wherein one of these sub-paths controls a pull-up device within output buffer 120, and the other sub-path controls a pull-down device within output buffer 120. With so many paths interweaving together, it is very hard to optimize the design such that all paths have the same delay to achieve minimal skew. The skew will be further magnified by process, voltage and temperature variation.
In addition, if synchronous output buffer circuit 100 operates from a different power supply than the associated internal logic, the voltage translation circuit within the output buffer circuit 100 introduces more delay skew over all of the possible voltage combinations of the internal logic power supply and the output buffer power supply. It is difficult to design the voltage translation circuit such that the delays introduced by logic ‘1’ to logic ‘0’ transitions are the same as the delays introduced by logic ‘0’ to logic ‘1’ transitions.
It would therefore be desirable to have an improved synchronous output buffer circuit, which overcomes the above-described deficiencies of the prior art, thereby minimizing the skew between output signals.